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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
D Low Supply Voltage Range 1.8 V - 3.6 V D Ultralow-Power Consumption:
- Active Mode: 200 A at 1 MHz, 2.2 V - Standby Mode: 0.7 A - Off Mode (RAM Retention): 0.1 A Five Power Saving Modes Wake-Up From Standby Mode in less than 6 s 16-Bit RISC Architecture, 125 ns Instruction Cycle Time Basic Clock Module Configurations: - Various Internal Resistors - Single External Resistor - 32-kHz Crystal - High Frequency Crystal - Resonator - External Clock Source 16-Bit Timer_A With Three Capture/Compare Registers 10-Bit, 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller
D Serial Onboard Programming,
No External Programming Voltage Needed Programmable Code Protection by Security Fuse Supply Voltage Brownout Protection MSP430x11x2 Family Members Include: MSP430F1122: 4KB + 256B Flash Memory 256B RAM MSP430F1132: 8KB + 256B Flash Memory 256B RAM Available in 20-Pin Plastic SOWB, 20-Pin Plastic TSSOP and 32-Pin QFN Packages MSP430x12x2 Family Members Include: MSP430F1222: 4KB + 256B Flash Memory 256B RAM MSP430F1232: 8KB + 256B Flash Memory 256B RAM Available in 28-Pin Plastic SOWB, 28-Pin Plastic TSSOP, and 32-Pin QFN Packages For Complete Module Descriptions, See the MSP430x1xx Family User's Guide, Literature Number SLAU049
D D D D
D D
D
D D
D
D Serial Communication Interface (USART0)
With Software-Selectable Asynchronous UART or Synchronous SPI (MSP430x12x2 Only)
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6s. The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal microcontrollers with a built-in 16-bit timer, 10-bit A/D converter with integrated reference and data transfer controller (DTC) and fourteen or twenty-two I/O pins. In addition, the MSP430x12x2 series microcontrollers have built-in communication capability using asynchronous (UART) and synchronous (SPI) protocols. Digital signal processing with the 16-bit RISC performance enables effective system solutions such as glass breakage detection with signal analysis (including wave digital filter algorithm). Another area of application is in stand-alone RF sensors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002 - 2003, Texas Instruments Incorporated
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 20-PIN SOWB (DW) PLASTIC 20-PIN TSSOP (PW) PLASTIC 28-PIN SOWB (DW) PLASTIC 28-PIN TSSOP (PW) PLASTIC 32-PIN QFN (RHB) MSP430F1122IRHB MSP430F1132IRHB MSP430F1222IRHB MSP430F1232IRHB
-40C to 85C
MSP430F1122IDW MSP430F1132IDW
MSP430F1122IPW MSP430F1132IPW
MSP430F1222IDW MSP430F1232IDW
MSP430F1222IPW MSP430F1232IPW
pin designation, MSP430x11x2 (see Note)
DW or PW PACKAGE (TOP VIEW)
TEST VCC P2.5/ROSC VSS XOUT XIN RST/NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK P2.4/TA2/A4/VREF+/VeREF+ P2.3/TA1/A3/VREF-/VeREF-
RHB PACKAGE (TOP VIEW)
VSS XOUT XIN NC RST/NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2
1 31 30 29 28 27 26 24 2 23 3 22 4 21 20 5 6 19 18 7 8 10 11 12 13 14 15 17
P2.5/ROSC NC VCC TEST P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK NC P2.4/TA2/A4/VREF+/VeREF+ P2.3/TA1/A3/VREF-/VeREF- NC
Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes, otherwise increased current consumption may occur. Power pad not internally connected. 2
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
pin designation, MSP430x12x2 (see Note)
DW or PW PACKAGE (TOP VIEW)
TEST VCC P2.5/ROSC VSS XOUT XIN RST/NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 P3.0/STE0/A5 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK P2.4/TA2/A4/VREF+/VeREF+ P2.3/TA1/A3/VREF-/VeREF- P3.7/A7 P3.6/A6 P3.5/URXD0 P3.4/UTXD0
RHB PACKAGE (TOP VIEW)
VSS XOUT XIN NC RST/NMI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2
26 24 1 31 30 29 28 27 2 23 3 22 4 21 20 5 6 19 18 7 8 10 11 12 13 14 15 17
P2.5/ROSC NC VCC TEST P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK/ADC10CLK NC P2.4/TA2/A4/VREF+/VeREF+ P2.3/TA1/A3/VREF-/VeREF- NC
Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes, otherwise increased current consumption may occur. Power pad not internally connected.
P3.0/STE0/A5 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/A6 P3.7/A7
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
functional block diagram, MSP430x11x2
XIN XOUT VCC VSS RST/NMI JTAG ROSC Oscillator System Clock ACLK SMCLK 8KB Flash 4KB Flash 256B RAM ADC10 10-Bit Autoscan DTC P1 P2
8 I/O Port 1 8 I/Os, with Interrupt Capability
6 I/O Port 2 6 I/Os, with Interrupt Capability
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
TEST
Watchdog Timer 15/16-Bit
Timer_A3 3 CC Reg
POR/ Brownout
functional block diagram, MSP430x12x2
XIN XOUT VCC VSS RST/NMI JTAG ROSC Oscillator System Clock ACLK SMCLK 8KB Flash 4KB Flash 256B RAM ADC10 10-Bit Autoscan DTC P1 P2 P3
8 I/O Port 1 8 I/Os, with Interrupt Capability
6 I/O Port 2 6 I/Os, with Interrupt Capability
8 I/O Port 3 8 I/Os
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
TEST
Watchdog Timer 15/16-Bit
Timer_A3 3 CC Reg
POR/ Brownout
USART0 UART Mode SPI Mode
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
Terminal Functions, MSP430x11x2
NAME P1.0/TACLK/ ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 P2.3/TA1/A3/VREF-/ VeREF- P2.4/TA2/A4/VREF+/ VeREF+ P2.5/ROSC RST/NMI TEST VCC VSS XIN XOUT NC TERMINAL DW & PW 13 14 15 16 17 18 19 20 8 9 10 11 12 3 7 1 2 4 6 5 NA RHB 21 22 23 24 25 26 27 28 6 7 8 18 19 32 5 29 30 1 3 2 4,9-16, 17,20,31 I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I DESCRIPTION General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion clock--10-bit ADC General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0 General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit ADC input A1 General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/analog input to 10-bit ADC input A2/BSL receive General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output/analog input to 10-bit ADC input A3/negative reference voltage terminal. General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit ADC input A4/I/O of positive reference voltage terminal General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency Reset or nonmaskable interrupt input Selects test mode for JTAG pins on P1.x Supply voltage Ground reference Input terminal of crystal oscillator Output terminal of crystal oscillator No connect. Recommended connection to VSS to avoid floating nodes, otherwise increased current consumption may occur.
TDO or TDI is selected via JTAG instruction.
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Terminal Functions, MSP430x12x2
NAME P1.0/TACLK/ ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P2.0/ACLK/A0 P2.1/INCLK/A1 P2.2/TA0/A2 P2.3/TA1/A3/VREF-/ VeREF- P2.4/TA2/A4/VREF+/ VeREF+ P2.5/ROSC P3.0/STE0/A5 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/A6 P3.7/A7 RST/NMI TEST VCC VSS XIN XOUT NC TERMINAL DW & PW 21 22 23 24 25 26 27 28 8 9 10 19 20 3 11 12 13 14 15 16 17 18 7 1 2 4 6 5 NA RHB 21 22 23 24 25 26 27 28 6 7 8 18 19 32 9 10 11 12 13 14 15 16 5 29 30 1 3 2 4,17, 20,31 I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I DESCRIPTION General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion clock--10-bit ADC General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal or test clock input General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0 General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit ADC input A1 General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/analog input to 10-bit ADC input A2/BSL receive General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output/analog input to 10-bit ADC input A3/negative reference voltage terminal. General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit ADC input A4/I/O of positive reference voltage terminal General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency General-purpose digital I/O pin/slave transmit enable--USART0/SPI mode/analog input to 10-bit ADC input A5 General-purpose digital I/O pin/slave in/master out of USART0/SPI mode General-purpose digital I/O pin/slave out/master in of USART0/SPI mode General-purpose digital I/O pin/external clock input--USART0/UART or SPI mode, clock output--USART0/SPI mode clock input General-purpose digital I/O pin/transmit data out--USART0/UART mode General-purpose digital I/O pin/receive data in--USART0/UART mode General-purpose digital I/O pin/analog input to 10-bit ADC input A6 General-purpose digital I/O pin/analog input to 10-bit ADC input A7 Reset or nonmaskable interrupt input Selects test mode for JTAG pins on P1.x Supply voltage Ground reference Input terminal of crystal oscillator Output terminal of crystal oscillator No connect. Recommended connection to VSS to avoid floating nodes, otherwise increased current consumption may occur.
TDO or TDI is selected via JTAG instruction.
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short-form description
CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Table 1. Instruction Word Formats
Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL e.g. JNE R8 R4 + R5 ---> R5 PC -->(TOS), R8--> PC Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source SD SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) M(MEM) --> M(TCDAT) M(R10) --> M(Tab+R6) M(R10) --> R11 R10 + 2--> R10 #45 --> M(TONI)
D D D D D D D
D D D D
D = destination
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:
D Active mode AM;
- All clocks are active
D Low-power mode 0 (LPM0);
- CPU is disabled ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
- CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO's dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
- CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator remains enabled ACLK remains active
D Low-power mode 3 (LPM3);
- CPU is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled ACLK remains active
D Low-power mode 4 (LPM4);
- CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO's dc-generator is disabled Crystal oscillator is stopped
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE Power-up, external reset, watchdog NMI, oscillator fault, flash memory access violation INTERRUPT FLAG WDTIFG (see Note1) KEYV (see Note 1) NMIIFG (see Notes 1 and 4) OFIFG (see Notes 1 and 4) ACCVIFG (see Notes 1 and 4) SYSTEM INTERRUPT Reset (Non)-maskable, (Non)-maskable, (Non)-maskable WORD ADDRESS 0FFFEh PRIORITY 15, highest
0FFFCh 0FFFAh 0FFF8h 0FFF6h
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0, lowest
Watchdog timer Timer_A Timer_A USART0 receive (see Note 5) USART0 transmit (see Note 5) ADC10
WDTIFG TACCR0 CCIFG (see Note 2) TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) URXIFG0 UTXIFG0 ADC10IFG P2IFG.0 to P2IFG.7 (see Notes 1 and 2) P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable Maskable Maskable Maskable Maskable Maskable
0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h
I/O Port P2 (eight flags - see Note 3) I/O Port P1 (eight flags)
Maskable Maskable
0FFE6h 0FFE4h 0FFE2h 0FFE0h
NOTES: 1. 2. 3. 4. 5.
Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0-5) are implemented on the '11x2 and '12x2 devices. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. USART0 is implemented in MSP430x12x2 only.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2
Address 0h 7 6 5 ACCVIE rw-0 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
WDTIE: OFIE: NMIIE: ACCVIE:
Address 01h
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault enable (Non)maskable interrupt enable Flash access violation interrupt enable
7 6 5 4 3 2 1 UTXIE0 rw-0 0 URXIE0 rw-0
URXIE0: USART0, UART, and SPI receive-interrupt enable (MSP430x12x2 devices only) UTXIE0: USART0, UART, and SPI transmit-interrupt enable (MSP430x12x2 devices only) interrupt flag register 1 and 2
Address 02h 7 6 5 4 NMIIFG rw-0 3 2 1 OFIFG rw-1 0 WDTIFG rw-0
WDTIFG: OFIFG: NMIIFG:
Address 03h
Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI-pin
7 6 5 4 3 2 1 UTXIFG0 rw-1 0 URXIFG0 rw-0
URXIFG0: USART0, UART, and SPI receive flag (MSP430x12x2 devices only) UTXIFG0: USART0, UART, and SPI transmit flag (MSP430x12x2 devices only)
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module enable registers 1 and 2
Address 04h 7 6 5 4 3 2 1 0
Address 05h
7
6
5
4
3
2
1 UTXE0 rw-0
0 URXE0 USPIE0 rw-0
URXE0: UTXE0: USPIE0:
Legend
USART0, UART mode receive enable (MSP430x12x2 devices only) USART0, UART mode transmit enable (MSP430x12x2 devices only) USART0, SPI mode transmit and receive enable (MSP430x12x2 devices only)
rw: rw-0: Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device.
memory organization
MSP430F1122 MSP430F1222 FFFFh FFE0h FFDFh F000h Int. Vector 4 KB Flash Segment0-7 FFFFh FFE0h FFDFh MSP430F1132 MSP430F1232 Int. Vector 8 KB Flash Segment0-15 Main Memory
E000h 10FFh 1000h 0FFFh 0C00h 2 x 128B Flash SegmentA,B 1 KB Boot ROM 10FFh 1000h 0FFFh 0C00h 2 x 128B Flash SegmentA,B 1 KB Boot ROM Information Memory
02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h
256B RAM 16b Per. 8b Per. SFR
02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h
256B RAM 16b Per. 8b Per. SFR
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
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bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSL Function MSP430x11x2 DW & PW Package (20 Pins) 14 - P1.1 10 - P2.2 MSP430x12x2 DW & PW Package (28 Pins) 22 - P1.1 10 - P2.2 MSP430x11x2/12x2 RHB Package (32 Pins) 22 - P1.1 8 - P2.2
Data Transmit Data Receive
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0F800h 0F7FFh 0F600h Segment0 w/ Interrupt Vectors Segment1 Segment2 Segment3 Segment4 Flash Main Memory Information Memory
0E3FFh 0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h
Segment14 Segment15 SegmentA SegmentB
NOTE: All segments not implemented on all devices.
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number SLAU049.
oscillator and system clock
The clock system in the MSP430x11x2 and MSP430x12x2 devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are 3 8-bit I/O ports implemented--ports P1, P2, and P3 (only six port P2 I/O signals are available on external pins; port P3 is implemented only on 'x12x2 devices):
D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2. Read/write access to port-control registers is supported by all instructions.
NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins, but all control and data bits for port P2 are implemented. Port P3 has no interrupt capability. Port P3 is implemented in MSP430x12x2 only.
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
USART0 (MSP430x12x2 Only)
The MSP430x12x2 devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention.
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timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_A3 Signal Connections Input Pin Number DW and PW '11x2 20-Pin 13 - P1.0 '12x2 28-Pin 21 - P1.0 RHB '11x2/12x2 32-Pin 21 - P1.0 Device Input Signal TACLK ACLK SMCLK 9 - P2.1 14 - P1.1 10 - P2.2 9 - P2.1 22 - P1.1 10 - P2.2 7 - P2.1 22 - P1.1 8 - P2.2 INCLK TA0 TA0 DVSS DVCC 15 - P1.2 11 - P2.3 23 - P1.2 19 - P2.3 23 - P1.2 18 - P2.3 TA1 TA1 DVSS DVCC 16 - P1.3 24 - P1.3 24 - P1.3 TA2 ACLK (internal) DVSS DVCC Module Input Name TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 CCR1 TA1 CCR0 TA0 14 - P1.1 18 - P1.5 10 - P2.2 15 - P1.2 19 - P1.6 11 - P2.3 16 - P1.3 20 - P1.7 12 - P2.4 22 - P1.1 26 - P1.5 10 - P2.2 ADC10 Internal 23 - P1.2 27 - P1.6 19 - P2.3 24 - P1.3 28 - P1.7 20 - P2.4 23 - P1.2 27 - P1.6 18 - P2.3 24 - P1.3 28 - P1.7 19 - P2.4 22 - P1.1 26 - P1.5 8 - P2.2 Timer NA Module Block Module Output Signal Output Pin Number DW and PW '11x2 20-Pin '12x2 28-Pin RHB '11x2/12x2 32-Pin
ADC10 Internal
ADC10 Internal
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peripheral file map
PERIPHERALS WITH WORD ACCESS ADC10 ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 ADC analog enable ADC data transfer control register 1 ADC data transfer control register 0 Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash control 3 Flash control 2 Flash control 1 Watchdog/timer control PERIPHERALS WITH BYTE ACCESS USART0 (in MSP430x12x2 only) Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Basic clock sys. control2 Basic clock sys. control1 DCO clock freq. control Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL BCSCTL2 BCSCTL1 DCOCTL P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 077h 076h 075h 074h 073h 072h 071h 070h 058h 057h 056h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE ADC10DTC1 ADC10DTC0 1BCh 1B4h 1B2h 1B0h 04Ah 049h 048h 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h
Timer_A
TACCR2 TACCR1 TACCR0 TAR
TACCTL2 TACCTL1 TACCTL0 TACTL TAIV FCTL3 FCTL2 FCTL1 WDTCTL
Flash Memory
Watchdog
Basic Clock
Port P2
Port P1
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P3 (in MSP430x12x2 only) Port P3 selection Port P3 direction Port P3 output Port P3 input Module enable2 Module enable1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 P3SEL P3DIR P3OUT P3IN ME2 ME1 IFG2 IFG1 IE2 IE1 01Bh 01Ah 019h 018h 005h 004h 003h 002h 001h 000h
Special Function
absolute maximum ratings
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN Supply voltage during program execution, VCC (see Note 1) Supply voltage during program/erase flash memory, VCC Supply voltage, VSS Operating free-air temperature range, TA LF mode selected, XTS=0 LFXT1 crystal frequency, f(LFXT1) (see Note 2) XT1 selected mode, XTS=1 MSP430F11x2 MSP430F12x2 Watch crystal Ceramic resonator Crystal VCC = 1.8 V, MSP430F11x2 MSP430F12x2 Processor frequency f(system) (MCLK signal) VCC = 3.6 V, MSP430F11x2 MSP430F12x2 450 1000 dc -40 32 768 8000 8000 4.15 MHz dc 8 MSP430F11x2 MSP430F12x2 1.8 2.7 0 85 NOM MAX 3.6 3.6 UNITS V V V C Hz kHz
NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 M from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC 2.2 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC 2.8 V. 2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MSP430F11x2 and MSP430F12x2 Devices
f (system) - Maximum Processor Frequency - MHz 9 8 MHz at 3.6 V 8 7 6 5 4 3 2 1 0 0 1 2 3 VCC - Supply Voltage - V 4 4.15 MHz at 1.8 V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V.
Figure 1. Frequency vs Supply Voltage supply current (into VCC) excluding external current
PARAMETER TEST CONDITIONS TA = -40C +85C, fMCLK = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz, Program executes in Flash TA = -40C +85C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz, Program executes in Flash I(CPUOff) Low-power mode, (LPM0) TA = -40C +85C, f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz TA = -40C +85C, f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 TA = -40C TA = 25C TA = 85C TA = -40C TA = 25C TA = 85C TA = -40C I(LPM4) Low-power mode, (LPM4) TA = 25C TA = 85C VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V MIN TYP 200 300 3 11 32 55 11 17 0.8 0.7 1.6 1.8 VCC = 3 V 1.6 2.3 0.1 0.1 0.8 MAX 250 A 350 5 18 45 70 14 22 1.2 1 2.3 2.2 1.9 3.4 0.5 0.5 1.9 A A A A UNIT
I(AM)
Active mode
A
I(LPM2)
Low-power mode, (LPM2)
A
I(LPM3)
Low-power mode, (LPM3)
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
current consumption of active mode versus system frequency IAM = IAM[1 MHz] x fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 120 A/V x (VCC-3 V) Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER VIT+ VIT- Vhys Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis, (VIT+ - VIT-) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.9 0.3 0.5 TYP MAX 1.5 1.9 0.9 1.3 1.1 1 V V V UNIT
standard inputs - RST/NMI; TEST
PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC = 2.2 V / 3 V MIN VSS 0.8xVCC TYP MAX VSS+0.6 VCC UNIT V V
inputs Px.x, TAx
PARAMETER TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1) VCC 2.2 V/3 V 2.2 V 3V 2.2 V t(cap) f(TAext) f(TAint) Timer_A, capture timing Timer_A clock frequency externally applied to pin Timer_A clock frequency TA0, TA1, TA2 3V 2.2 V 3V 2.2 V SMCLK or ACLK signal selected 3V MIN 1.5 62 50 62 50 8 10 8 10 MHz ns ns TYP MAX UNIT cycle
t(int)
External interrupt timing
TACLK, INCLK t(H) = t(L)
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles.
leakage current
PARAMETER TEST CONDITIONS Port P1: P1.x, 0 x 7 (see Notes 1 and 2) Ilkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 x 5 (see Notes 1 and 2) VCC 2.2 V/3 V 2.2 V/3 V MIN TYP MAX 50 nA 50 UNIT
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA I(OHmax) = -6 mA I(OHmax) = -1.5 mA I(OHmax) = -6 mA I(OLmax) = 1.5 mA I(OLmax) = 6 mA I(OLmax) = 1.5 mA See Note 1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 UNIT
VOH
High-level output voltage
V
VOL
Low-level output voltage
V
I(OLmax) = 6 mA See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
outputs P1.x, P2.x, P3.x, TAx
PARAMETER f(P20) f(TAx) Output frequency TEST CONDITIONS P2.0/ACLK, CL = 20 pF TA0, TA1, TA2, CL = 20 pF, Internal clock source, SMCLK signal applied (see Note 1) fSMCLK = fLFXT1 = fXT1 P1.4/SMCLK, CL = 20 pF t(Xdc) Duty cycle of O/P frequency P2.0/ACLK, CL = 20 pF fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK fP20 = fLFXT1 = fXT1 fP20 = fLFXT1 = fLF fP20 = fLFXT1/n 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V VCC 2.2 V/3 V 2.2 V/3 V MIN TYP MAX fSystem dc 40% 35% 50%- 15 ns 50%- 15 ns 40% 30% 50% 50 ns 50% 50% fSystem 60% 65% 50%+ 15 ns 50%+ 15 ns 60% 70% MHz UNIT
t(TAdc) TA0, TA1, TA2, CL = 20 pF, Duty cycle = 50% 2.2 V/3 V 0 NOTES: 1. The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, and P3 (see Note)
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 32 28 24 20 16 12 8 4 0 0.0 VCC = 2.2 V P1.0 TA = 25C 50 VCC = 3 V P1.0 40 TA = 25C TA = 85C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
TA = 85C
30
20
10
0.5
1.0
1.5
2.0
2.5
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL - Low-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA 0 -4 -8 -12 -16 -20 TA = 85C -24 TA = 25C -28 0.0 0.5 1.0 1.5 2.0 2.5 VCC = 2.2 V P1.0 0 VCC = 3 V P1.0 -10
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
-20
-30
-40
TA = 85C
-50
TA = 25C
-60 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH - High-Level Output Voltage - V
VOH - High-Level Output Voltage - V
Figure 4
NOTE: Only one output is loaded at a time.
Figure 5
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
USART (see Note 1)
PARAMETER t() () USART: deglitch time TEST CONDITIONS VCC = 2.2 V VCC = 3 V MIN 200 150 TYP 430 280 MAX 800 500 UNIT ns
NOTES: 1. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line.
RAM
PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTES: 1. This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition.
POR brownout, reset (see Notes 1 and 2)
PARAMETER td(BOR) VCC(start) V(B_IT-) Vhys(B_IT-) t(reset) Brownout dVCC/dt 3 V/s dVCC/dt 3 V/s dVCC/dt 3 V/s 70 TEST CONDITIONS MIN TYP 0.7 x V(B_IT-) 1.71 130 180 MAX 2000 UNIT s V V mV
Pulse length needed at RST/NMI pin to accepted reset internally, 2 s VCC = 2.2 V/3 V NOTES: 1. The current consumption of the brown-out module is already included in the ICC current consumption data. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min). See the MSP430x1xx Family User's Guide for more information on the brownout circuit.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
VCC Vhys(B_IT-) V(B_IT-) VCC(start)
1 Set signal for POR circuitry 0
td(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
2 V cc = 3.0 V Typical Conditions VCC(min)- V 1.50 1 0.50 0 0.001 VCC(min) VCC 3V t pw
1 tpw - Pulse Width - s
1000 1ns 1ns tpw - Pulse Width - s
Figure 7. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC 2 VCC(min)- V 1.50 1 VCC(min) 0.50 0 0.001 tfall = trise 1 tpw - Pulse Width - s 1000 tfall trise tpw - Pulse Width - s V cc = 3.0 V Typical Conditions 3V t pw
Figure 8. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
crystal oscillator,LFXT1
PARAMETER Pin load capacitance TEST CONDITIONS XTS=0; LF mode selected XTS=1; XT1 mode selected (see Note 1) XTS=0; LF mode selected XTS=1; XT1 mode selected (see Note 1) see Note 2 VCC 2.2 V / 3 V 2.2 V / 3 V 2.2 V / 3 V 2.2 V / 3 V 2.2 V / 3 V VSS 0.8 x VCC MIN TYP 12 pF 2 12 2 0.2 x VCC VCC pF V V MAX UNIT
CXIN
CXOUT VIL VIH
Pin load capacitance Input levels at XIN
NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
DCO
PARAMETER f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO77) f(DCO47) S(Rsel) S(DCO) Dt DV TEST CONDITIONS Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, SR = fRsel+1/fRsel SDCO = fDCO+1/fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C VCC 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V 2.2 V/3 V MIN 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 4 4.4 fDCO40 x1.7 1.35 1.07 -0.31 -0.33 TYP 0.12 0.13 0.19 0.18 0.3 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2 2.9 3.2 4.5 4.9 fDCO40 x2.1 1.65 1.12 -0.36 -0.38 MAX 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.9 1.5 1.5 2.2 2.29 3.4 3.65 4.9 5.4 fDCO40 x2.5 2 1.16 -0.4 -0.43 5 %/C %/V ratio MHz MHz MHz MHz MHz UNIT
MHz
MHz
MHz
MHz
MHz
NOTES: 1. These parameters are not production tested.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
Frequency Variance
f(DCOx7)
Max Min
f(DCOx0)
Max Min
1 f DCOCLK
principle characteristics of the DCO
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
fDCOx0 to fDCOx7 are valid for all devices.
D The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO. D The modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK
cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO x (2MOD/32).
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7.
wake-up from lower power modes (LPMx)
PARAMETER t(LPM0) t(LPM2) t(LPM3) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, f(MCLK) = 3 MHz, f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V MIN TYP 100 100 6 6 6 6 6 6 s s ns MAX UNIT
Delay time (see Note 1)
t(LPM4)
f(MCLK) = 3 MHz, NOTES: 1. Parameter applicable only if DCOCLK is used for MCLK.
24
IIIIII IIIIII IIIIII IIIIII
2.2 V 3V VCC
0
1
2
3
4
5
6
7
DCO Steps
Figure 9. DCO Characteristics
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER VCC V(P6.x/Ax) Analog supply voltage Analog input voltage range (see Note 2) Operating supply current into VCC terminal (see Note 3) Reference operating supply current, reference buffer disabled (see Note 4) Reference buffer operating supply current (see Note 4) Input capacitance TEST CONDITIONS VSS = 0 V All Ax terminals. Analog inputs selected in ADC10AE register and PxSel.x=1 VSS VPx.x/Ax VCC fADC10CLK = 5.0 MHz ADC10ON = 1, REFON = 0 ADC10SHT0=1, ADC10SHT1=0, ADC10DIV=0 fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = x; REFOUT = 0 fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = 0 REFOUT = 1 Only one terminal can be selected at one time, Px.x/Ax 2.2 V 3V MIN 2.2 0 NOM MAX 3.6 VCC 0.52 0.6 1.05 mA 1.2 UNIT V V
IADC10
IREF+
2.2V/3 V
0.25
0.4
mA
ADC10SR = 0 ADC10SR = 1 2.2 V
1.1 0.46
1.4 mA 0.55 27 pF
IREFB
CI
RI Input MUX ON resistance 0V VAx VCC 3V 2000 Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC10. 4. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
10-bit ADC, external reference (see Note 1)
PARAMETER VeREF+ VREF- /VeREF- (VeREF+ - VREF-/VeREF-) IVeREF+ IVREF-/VeREF- Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input Static input current Static input current TEST CONDITIONS VeREF+ > VREF-/VeREF- (see Note 2) VeREF+ > VREF-/VeREF- (see Note 3) VeREF+ > VREF-/VeREF- (see Note 4) 0V VeREF+ VCC 0V VeREF- VCC 2.2 V/3 V 2.2 V/3 V MIN 1.4 0 1.4 NOM MAX VCC 1.2 VCC 1 1 UNIT V V V A A
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, built-in reference
PARAMETER Positive built-in reference voltage output TEST CONDITIONS REF2_5V = 1 for 2.5 V IVREF+ IVREF+max REF2_5V = 0 for 1.5 V IVREF+ IVREF+max REF2_5V = 0, IVREF+ 1mA REF2_5V = 1, IVREF+ 0.5mA REF2_5V = 1, IVREF+ 1mA 2.2 V 3V IVREF+ = 500 A +/- 100 A Analog input voltage ~0.75 V; REF2_5V = 0 IVREF+ = 500 A 100 A Analog input voltage ~1.25 V; REF2_5V = 1 IVREF+ =100 A 900 A, VCC=3 V, Ax ~0.5 x VREF+ Error of conversion result 1 LSB REFON =1, IVREF+ 1 mA IVREF+ is a constant in the range of 0 mA IVREF+ 1 mA 2.2 V 3V 3V ADC10SR = 0 ADC10SR = 1 2.2 V/3 V 2.2 V/3 V 3V 2.2 V/3 V MIN 2.35 1.41 2.2
VREF+ + 0.15 VREF+ + 0.15
NOM 2.5 1.5
MAX 2.65
UNIT
VREF+
V 1.59
VCC(min)
VCC minimum voltage, Positive built-in reference active Load current out of VREF+ terminal
V 0.5 1 2 2 2 400 ns 2000 100 100 30 0.8 s s pF ppm/C LSB
IVREF+
mA
IL(VREF)+
Load-current regulation VREF+ terminal
LSB
tDL(VREF) + CVREF+ TREF+
Load current regulation VREF+ terminal Capacitance at pin VREF+ (see Note 1) Temperature coefficient of built-in reference Settle time of internal reference voltage and VREF+ (see Note 2)
tREFON
IVREF+ = 0.5 mA,VREF+ = 1.5 V, VCC = 3.6 V, REFON = 0 1 IVREF+ = 0.5 mA, VREF+ = 1.5 V, VCC = 2.2 V, REFON = 1 ADC10SR = 0
ADC10SR = 1 2.5 Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1), must be limited; the reference buffer may become unstable otherwise. NOTES: 2. The condition is that the error in a conversion started after tREFON is less than 0.5 LSB.
26
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters
PARAMETER fADC10CLK fADC10OSC TEST CONDITIONS Error of conversion result 1 LSB ADC10DIV=0, fADC10CLK=fADC10OSC Internal oscillator, fADC10OSC = 3.7 MHz to 6.3 MHz ADC10SR = 0 ADC10SR = 1 2.2 V/ 3V MIN 0.450 0.450 3.7 NOM MAX 6.3 1.5 6.3 MHz MHz s s 100 3V 2.2 V 1400 1400 ns ns UNIT
2.2 V/ 3 V
2.06 13xADC10DIVx 1/fADC10CLK
3.51
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK or SMCLK: ADC10SSEL 0 tADC10ON tSample Turn on settling time of the ADC Sampling time (see Note 1) RS = 400 , RI = 2000 , CI = 20 pF (see Note 2)
Not production tested, limits characterized Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already settled. 2. Approximately eight Tau () are needed to get an error of less than 0.5 LSB. tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, RS = external source resistance) tSample = ln(2n+1) x (RS + RI) x CI+ 2.5 s. (ADC10SR = 1, n = ADC resolution = 10, RS = external source resistance)
10-bit ADC, linearity parameters
PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error Gain error Total unadjusted error TEST CONDITIONS 1.4 V (VeREF+ - VREF-/VeREF-) min 1.6 V 1.6 V < (VeREF+ - VREF-/VeREF-) min [VCC] (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), Internal impedance of source RS < 100 , (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2 1.1 2 MIN NOM MAX 1 1 1 4 2 5 UNIT LSB LSB LSB LSB LSB
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in VMID
PARAMETER ISENSOR VSENSOR TCSENSOR tSENSOR(sample) IVMID VMID tVMID(sample) Sample time required if channel 10 is selected (see Note 2) Current into divider at channel 11 (see Note 3) VCC divider at channel 11 Sample time required if channel 11 is selected (see Note 4) Operating supply current into VCC terminal (see Note 1) TEST CONDITIONS REFON = 0, INCH = 0Ah, ADC10ON=NA, TA = 25_C ADC10ON = 1, INCH = 0Ah, TA = 0C ADC10ON = 1, INCH = 0Ah ADC10ON = 1, INCH = 0Ah, Error of conversion result 1 LSB ADC10ON = 1, INCH = 0Bh, ADC10ON = 1, INCH = 0Bh, VMID is ~0.5 x VCC ADC10ON = 1, INCH = 0Bh, Error of conversion result 1 LSB 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 1400 1220 1.1 1.5 30 30 NA NA 1.10.04 1.500.04 V ns MIN NOM 40 60 986 986 3.55 3.55 MAX 120 160 9865% 9865% 3.553% 3.553% mV/C s s A A mV UNIT A A
Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal is high). Therefore it includes the constant current through the sensor and the reference. 2. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). 3. No additional current is needed. The VMID is used during sampling. 4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER VCC(PGM/ ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, 0 tBlock, 1-63 tBlock, End tMass Erase tSeg Erase TEST CONDITIONS VCC MIN NOM MAX UNIT
Program and Erase supply voltage Flash Timing Generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time Cumulative mass erase time Program/Erase endurance Data retention duration Word or byte program time Block program time for 1st byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time see Note 3 TJ = 25C see Note 1 see Note 2 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V
2.7 257 3 3 200 104 100 35 30 21 6 5297 4819
3.6 476 5 7 4 105
V kHz mA mA ms ms cycles years
tFTG
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write feature is used. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller's state machine; tFTG = 1/fFTG.
JTAG Interface
PARAMETER fTCK RInternal TCK input frequency Internal pull-up resistance on TMS, TCK, TDI/TCLK TEST CONDITIONS see Note 1 see Note 2 VCC 2.2 V 3V 2.2 V/ 3 V MIN 0 0 25 60 NOM MAX 5 10 90 UNIT MHz MHz k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all Flash versions.
JTAG Fuse (see Note 1)
PARAMETER VCC(FB) VFB IFB tFB Supply voltage during fuse-blow condition Voltage level on TEST for fuse-blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C VCC MIN 2.5 6 7 100 1 NOM MAX UNIT V V mA ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT 0 1 0 1 P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 Pad Logic
P1IN.x EN Module X IN P1IRQ.x D
P1IE.x P1IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select
P1IES.x P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1 DIRECTION CONTROL FROM MODULE P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3
PnSel.x P1Sel.0 P1Sel.1 P1Sel.2 P1Sel.3
PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3
PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3
MODULE X OUT ADC10CLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3
MODULE X IN TACLK CCI0A CCI1A CCI2A
PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3
PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3
PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3
Signal from or to Timer_A
30
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT 0 1 0 1 Pad Logic P1.4-P1.7
TST P1IN.x EN Module X IN D DVCC Bus Keeper
P1IRQ.x
P1IE.x P1IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select P1IES.x P1SEL.x Control by JTAG
60 k Typical
TEST
Bum and Test Fuse
P1.x TDO Controlled By JTAG
P1.7/TA2/TDO/TDI Controlled by JTAG TDI TST P1.x
P1.6/TA1/TDI/TCLK
NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. DIRECTION CONTROL FROM MODULE P1DIR.4 P1DIR.5 P1DIR.6
TST TMS
P1.x
P1.5/TA0/TMS TST TCK P1.4/SMCLK/TCK P1.x
PnSel.x P1Sel.4 P1Sel.5 P1Sel.6
PnDIR.x P1DIR.4 P1DIR.5 P1DIR.6
PnOUT.x P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7
MODULE X OUT SMCLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.4 P1IN.5 P1IN.6 P1IN.7
MODULE X IN unused unused unused unused
PnIE.x P1IE.4 P1IE.5 P1IE.6 P1IE.7
PnIFG.x P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7
PnIES.x P1IES.4 P1IES.5 P1IES.6 P1IES.7
P1Sel.7 P1DIR.7 P1DIR.7 Signal from or to Timer_A
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31
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
a0, or a1, or a2 selected in ADC10 a0, or a1, or a2 to ADC10, ADC10AE.x P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X Out 0 1 0 1 Bus Keeper P2.0/ACLK/A0 P2.1/INCLK/A1 P2IN.x EN Module X In P2.2/TA0/A2 0: input 1: output Pad Logic
D
P2IE.x P2IRQ.x P2IFG.x Q EN Set Interrupt Edge Select
NOTE: 0 x 2 DIRECTION CONTROL FROM MODULE P2DIR.0 P2DIR.1 P2DIR.2
P2IES.x
P2SEL.x
PnSel.x P2Sel.0 P2Sel.1 P2Sel.2 Timer_A
PnDIR.x P2DIR.0 P2DIR.1 P2DIR.2
PnOUT.x P2OUT.0 P2OUT.1 P2OUT.2
MODULE X OUT ACLK VSS OUT0 signal
PnIN.x P2IN.0 P2IN.1 P2IN.2
MODULE X IN unused INCLK CCI0B
PnIE.x P2IE.0 P2IE.1 P2IE.2
PnIFG.x P2IFG.0 P2IFG.1 P2IFG.2
PnIES.x P1IES.0 P1IES.1 P1IES.2
32
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
a3 Selected to ADC10, a3 ADC10AE.3 P2SEL.3 P2DIR.3 P2DIR.3 P2OUT.3 Module X Out P2IN.4 EN 0 1 0 1 Bus Keeper P2.3/ TA1/ A3/ V REF- /V eREF- 0: input 1: output Pad Logic
Module X In
D P2IE.4
P2IRQ.07 P2IFG.4
Q
EN Set
Interrupt Edge Select Reference Circuit in ADC10 Module P2IES.x P2SEL.x a10 on REFON ON ON REF_x Typ. 1.25 V
AVCC REF+
AVCC OUT 0 0,4 1,5 2_5 V
AV SS
+ _
0
1
SREF SREF.2 ADC10 ADC10 CTL0.12..14) CTL0.14) V+ V- R R
a4 Selected to ADC10, a4 ADC10AE.4 P2SEL.4 P2DIR.4 P2DIR.4 P2OUT.4 Module X Out P2IN.4 EN 0 1 0 1 Bus Keeper
Pad Logic
0: input 1: output
Unused
D P2IE.4 Interrupt Edge Select
P2.4/ TA2/ A4/ V REF+ / V eREF+
P2IRQ.07 P2IFG.4
Q
EN Set
P2IES.4
P2SEL.4
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33
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger (continued)
PnSel.x P2Sel.3 P2Sel.4 Timer_A PnDIR.x P2DIR.3 P2DIR.4 DIRECTION CONTROL FROM MODULE P2DIR.3 P2DIR.4 PnOUT.x P2OUT.3 P2OUT.4 MODULE X OUT Out1 signal Out2 signal PnIN.x P2IN.3 P2IN.4 MODULE X IN CCI1B Unused PnIE.x P2IE.3 P2IE.4 PnIFG.x P2IFG.3 P2IFG.4 PnIES.x P1IES.3 P1IES.4
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock Module
P2SEL.5 0 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT 1 0 1 0: Input 1: Output Pad Logic
P2.5/ROSC
P2IN.5
Bus Keeper
EN Module X IN D
P2IRQ.5
P2IE.5 P2IFG.5 Q EN Set Interrupt Flag
Interrupt Edge Select
Internal to Basic Clock Module 0 VCC
1
P2IES.5
DCOR
P2SEL.5 NOTE: DCOR: Control bit from Basic Clock Module: if it is set P2.5 is disconnected from P2.5 pad.
DC Generator
PnSel.x P2Sel.5
PnDIR.x P2DIR.5
DIRECTION CONTROL FROM MODULE P2DIR.5
PnOUT.x P2OUT.5
MODULE X OUT VSS
PnIN.x P2IN.5
MODULE X IN unused
PnIE.x P2IE.5
PnIFG.x P2IFG.5
PnIES.x P2IES.5
34
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x 0 P2DIR.x Direction Control From Module P2OUT.x Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN D 1 0 1 0: Input 1: Output
P2IRQ.x
P2IE.x P2IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select
PUC
P2IES.x P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2Sel.6 P2Sel.7 P2DIR.x P2DIR.6 P2DIR.7 DIRECTION CONTROL FROM MODULE P2DIR.6 P2DIR.7 P2OUT.x P2OUT.6 P2OUT.7 MODULE X OUT VSS VSS P2IN.x P2IN.6 P2IN.7 MODULE X IN unused unused P2IE.x P2IE.6 P2IE.7 P2IFG.x P2IFG.6 P2IFG.7 P2IES.x P2IES.6 P2IES.7
NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software interrupts.
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35
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.0, P3.6 and P3.7 input/output with Schmitt-trigger
a5, or a6, or a7 selected in ADC10 To ADC10 a5, or a6, or a7 ADC10AE.x P3SEL.x P3DIR.x Direction Control From Module P3OUT.x Module X Out 0 1 0 1 Bus Keeper P3.0/STE0/A5 P3.6/A6 P3IN.x EN Module X In P3.7/A7 Pad Logic 0: input 1: output
D
NOTE: x (0,6,7) Direction Control From Module VSS P3DIR.6 P3DIR.7
PnSel.x P3Sel.0 P3Sel.6 P3Sel.7 USART0
PnDIR.x P3DIR.0 P3DIR.1 P3DIR.2
PnOUT.x P3OUT.0 P3OUT.6 P3OUT.7
Module X OUT VSS VSS VSS
PnIN.x P3IN.0 P3IN.6 P3IN.7
Module X IN STE0 Unused Unused
36
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.1 input/output with Schmitt-trigger
P3SEL.1 SYNC MM STC STE P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART0 0 1 Pad Logic 0 1 P3.1/SIMO0 0: Input 1: Output
P3IN.1 EN SI(MO)0 To USART0 D
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2 SYNC MM STC STE P3DIR.2 DCM_SOMI P3OUT.2 SO(MI)0 From USART0 0 1 Pad Logic 0 1 P3.2/SOMI0 0: Input 1: Output
P3IN.2 EN (SO)MI0 To USART0 D
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37
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION input/output schematic (continued)
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3 SYNC MM STC STE P3DIR.3 DCM_UCLK P3OUT.3 UCLK.0 From USART0 0 1 Pad Logic 0 1 P3.3/UCLK0 0: Input 1: Output
P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
port P3, P3.4, and P3.5 input/output with Schmitt-trigger
P3SEL.x P3DIR.x Direction Control From Module 0 1 Pad Logic P3OUT.x Module X OUT 0 1 P3.4/UTXD0 P3.5/URXD0 0: Input 1: Output
P3IN.x EN Module X IN x {4,5} DIRECTION CONTROL FROM MODULE VCC VSS D
PnSel.x P3Sel.4
PnDIR.x P3DIR.4
PnOUT.x P3OUT.4 P3OUT.5
MODULE X OUT UTXD0 VSS
PnIN.x P3IN.4 P3IN.5
MODULE X IN Unused URXD0
P3Sel.5 P3DIR.5 Output from USART0 module Input to USART0 module
38
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MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
APPLICATION INFORMATION
JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 10). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).
Time TMS Goes Low After POR TMS
ITEST
ITF
Figure 10. Fuse Check Mode Current, MSP430F11x2, MSP430F12x2 The JTAG pins are terminated internally, and therefore do not require external termination.
NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information.
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39
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
MECHANICAL DATA
DW (R-PDSO-G**)
16 PINS SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0-8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000 / D 01/00
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
40
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0-8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
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41
MSP430x11x2, MSP430x12x2 MIXED SIGNAL MICROCONTROLLER
SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003
RHB (S-PQFP-N32)
A B 5,00
PLASTIC QUAD FLATPACK
32
PIN 1 INDEX AREA
1,00 0,80
0,08 C 0,05 MAX
PIN 1 IDENTIFIER 1 0,23 0,18 0,23 32
0,18 0,50 EXPOSED THERMAL DIE PAD D
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. QFN (Quad Flatpack No-Lead) Package configuration. D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected ground leads. E. Falls within JEDEC MO-220.
42
POST OFFICE BOX 655303
CCCCC CCCCC CCCCC CCCCC CCCCC
1 0,20 REF C SEATING PLANE 3,25 SQ 3,00 32X 0,50 0,30 4X 3,50 32X 0,30 0,18 0,10 M C A B 4204326/A 04/02
5,00
* DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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